Device for probe card power bus noise reduction
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United States of America Patent
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Feb 28, 2006
Grant Date -
N/A
app pub date -
Mar 1, 2005
filing date -
Mar 1, 2005
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor 'booster' bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.
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