Application-specific methods useful for testing look up tables in programmable logic devices
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United States of America Patent
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Feb 28, 2006
Issued Date -
N/A
app pub date -
Mar 12, 2003
filing date -
Aug 7, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given customer design without requiring the vendor to understand the design.
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