Optimization of routing layers and board space requirements for a ball grid array package
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United States of America Patent
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Mar 7, 2006
Grant Date -
Apr 14, 2005
app pub date -
Aug 19, 2004
filing date -
Feb 25, 2003
priority date (Note) -
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Abstract
A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid array package is described. The ball grid array package includes a substrate material having a first side configured to receive a semiconductor chip and a second side having a plurality of conductive pads arranged in an array of rows and columns. The array of pads has at least one edge not fully populated with pads.
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