Address sequencer within BIST (Built-in-Self-Test) system
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United States of America Patent
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Mar 7, 2006
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N/A
app pub date -
Jul 22, 2002
filing date -
Jul 22, 2002
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Abstract
An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.
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