Parallel design processes for integrated circuits
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United States of America Patent
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-
Mar 7, 2006
Grant Date -
May 26, 2005
app pub date -
Dec 21, 2004
filing date -
Jul 25, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a parallel design process for ICs, plural circuit features to be evaluated are laid out while designing an IC. Plural ICs are then fabricated and packaged. For a first packaged IC, an interior circuit feature coupled to at least one of the plural circuit features to be evaluated is identified. A trimming point on the interior circuit feature is identified using an x-ray inspection system; coordinates of the trimming point are related to coordinates of a visible reference marker; and the relationship between the visible reference marker and the trimming point is used to position a cutting tool over the trimming point. The cutting tool is used to cut into the first packaged IC until the interior circuit feature has been acceptably modified at the trimming point. Operation of the first packaged IC is compared to operation of a second packaged IC. Other parallel design processes are also disclosed.
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