Apparatus and method for managing a processor pipeline in response to exceptions
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United States of America Patent
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Mar 14, 2006
Grant Date -
Dec 30, 2004
app pub date -
Jun 24, 2003
filing date -
Jun 24, 2003
priority date (Note) -
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Abstract
The present invention is generally directed to an apparatus and method for performing a partial flush of a processor pipeline in response to exceptions (e.g., interrupts). In accordance with an aspect of one embodiment a processor is provided with logic that operates to flush only limited stages of a processor pipepline (e.g., stages between the current instruction and the pending interrupt) if the execution of a current instruction will impact the execution of a pending interrupt (e.g., if the current instruction is a branch, if the current instruction would cause the processor to enter a mode that disables the pending interrupt, etc.). In accordance with another aspect of this embodiment, a method is provided for performing a partial flush of processor pipeline if the execution of a current instruction would impact the execution of a pending interrupt.
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