Attestation key memory device and bus
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Mar 14, 2006
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N/A
app pub date -
Mar 31, 2000
filing date -
Mar 31, 2000
priority date (Note) -
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Abstract
In an embodiment of the present invention, a technique is provided for remote attestation. An interface maps a device via a bus to an address space of a chipset in a secure environment for an isolated execution mode. The secure environment is associated with an isolated memory area accessible by at least one processor. The at least one processor operates in one of a normal execution mode and the isolated execution mode. A communication storage corresponding to the address space allows the device to exchange security information with the at least one processor in the isolated execution mode in a remote attestation.
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