Assemblies displaying differential negative resistance
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United States of America Patent
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Mar 21, 2006
Grant Date -
Jan 15, 2004
app pub date -
Jul 10, 2002
filing date -
Jul 10, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at least about 9. The invention also includes a semiconductor construction comprising a substrate, and a first layer over the substrate. The first layer comprises Ge and one or more of S, Te and Se. A second layer is over the first layer. The second layer comprises M and A, where M is a transition metal and A is one or more of O, S, Te and Se. A third layer is over the second layer, and comprises Ge and one or more of S, Te and Se. The first, second and third layers are together incorporated into an assembly displaying differential negative resistance. Additionally, the invention includes methodology for forming assemblies displaying differential negative resistance, such as tunnel diode assemblies.
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