US Patent No: 7,016,989

Number of patents in Portfolio can not be more than 2000

Fast 16 bit, split transaction I/O bus

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Abstract

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A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as to the skew is distributed over multiple clock periods.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTEL CORPORATIONSANTA CLARA, CA26599

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bell, D Michael Beaverton, OR 25 858

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
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CIRRUS LOGIC, INC. (1)
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HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP (2)
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Datapoint Corporation (1)
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RADIUS INC. (1)
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APPLE INC. (2)
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GOOGLE TECHNOLOGY HOLDINGS LLC (1)
5,541,919 Multimedia multiplexing device and method using dynamic packet segmentation 155 1994
 
KABUSHIKI KAISHA TOSHIBA (1)
* 6,330,650 Data receiver that performs synchronous data transfer with reference to memory module 22 1998
 
INTELLECTUAL VENTURES II LLC (1)
5,768,546 Method and apparatus for bi-directional transfer of data between two buses with different widths 78 1996
 
MARCONI COMMUNICATIONS, INC. (1)
5,905,766 Synchronizer, method and system for transferring data 45 1996
 
RAYTHEON COMPANY (1)
4,719,621 Packet fastbus 64 1985
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (6)
5,257,258 "Least time to reach bound" service policy for buffer systems 11 1991
5,448,708 System for asynchronously delivering enqueue and dequeue information in a pipe interface having distributed, shared memory 17 1992
5,634,015 Generic high bandwidth adapter providing data communications between diverse communication networks and computer system 132 1994
5,671,441 Method and apparatus for automatic generation of I/O configuration descriptions 86 1994
5,715,438 System and method for providing time base adjustment 28 1995
5,768,550 Bus interface logic system 15 1995
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
5,668,971 Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data transfer 118 1996
 
LSI LOGIC CORPORATION (1)
5,210,858 Clock division chip for computer system which interfaces a slower cache memory controller to be used with a faster processor 22 1989
 
LUCENT TECHNOLOGIES INC. (1)
4,922,486 User to network interface protocol for packet communications networks 335 1988
 
TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) (1)
5,361,252 Method and a device for monitoring channel split data packet transmission 17 1993
 
Dell USA, L.P. (1)
5,657,457 Method and apparatus for eliminating bus contention among multiple drivers without performance degradation 8 1994
 
LENOVO (SINGAPORE) PTE LTD. (1)
5,325,492 System for asynchronously delivering self-describing control elements with a pipe interface having distributed, shared memory 61 1993
 
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MOTOROLA, INC. (1)
5,751,969 Apparatus and methods for predicting and managing congestion in a network 52 1995
 
ROUND ROCK RESEARCH, LLC (1)
* 6,044,474 Memory controller with buffered CAS/RAS external synchronization capability for reducing the effects of clock-to-signal skew 28 1997
 
National Semiconductor Corporation (1)
5,101,347 System for reducing skew in the parallel transmission of multi-bit data slices 19 1988
 
XLNT Designs, Inc. (1)
5,659,718 Synchronous bus and bus interface device 83 1994
 
INTEL CORPORATION (10)
5,404,171 Method and apparatus for synchronizing digital packets of information to an arbitrary rate 17 1992
5,471,587 Fractional speed bus coupling 40 1992
5,548,733 Method and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus system 26 1994
5,625,779 Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge 41 1994
5,894,567 Mechanism for enabling multi-bit counter values to reliably cross between clocking domains 11 1995
5,758,166 Method and apparatus for selectively receiving write data within a write buffer of a host bridge 28 1996
5,768,545 Collect all transfers buffering mechanism utilizing passive release for a multiple bus environment 14 1996
5,729,760 System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode 132 1996
5,784,579 Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth 11 1996
* 6,347,351 Method and apparatus for supporting multi-clock propagation in a computer system having a point to point half duplex interconnect 15 1999
 
Amdahl Corporation (1)
5,491,799 Communication interface for uniform communication among hardware and software units of a computer system 17 1994
* Cited By Examiner

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