Fast 16 bit, split transaction I/O bus

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7016989
SERIAL NO

09471445

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as to the skew is distributed over multiple clock periods.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTEL CORPORATIONSANTA CLARA, CA28362

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bell, D Michael Beaverton, OR 25 870

Cited Art Landscape

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* Cited By Examiner

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