Fast 16 bit, split transaction I/O bus

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7016989
SERIAL NO

09471445

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as to the skew is distributed over multiple clock periods.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTEL CORPORATIONSANTA CLARA, CA27836

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bell, D Michael Beaverton, OR 25 867

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
5193090 Access protection and priority control in distributed queueing 36 1990
 
CIRRUS LOGIC, INC. (1)
5771356 Apparatus for controlling FIFO buffer data transfer by monitoring bus status and FIFO buffer thresholds 77 1995
 
HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP (2)
5802278 Bridge/router architecture for high performance scalable networking 287 1996
5862338 Polling system that determines the status of network ports and that stores values indicative thereof 98 1996
 
Datapoint Corporation (1)
4941089 Input/output network for computer system 174 1986
 
RADIUS INC. (1)
5574862 Multiprocessing system with distributed input/output management 40 1993
 
APPLE INC. (2)
5467464 Adaptive clock skew and duty cycle compensation for a serial data bus 69 1993
5499338 Bus system having a system bus, an internal bus with functional units coupled therebetween and a logic unit for use in such system 11 1994
 
KABUSHIKI KAISHA TOSHIBA (1)
* 6330650 Data receiver that performs synchronous data transfer with reference to memory module 23 1998
 
INTELLECTUAL VENTURES II LLC (1)
5768546 Method and apparatus for bi-directional transfer of data between two buses with different widths 79 1996
 
MARCONI COMMUNICATIONS, INC. (1)
5905766 Synchronizer, method and system for transferring data 45 1996
 
GOOGLE INC. (1)
5541919 Multimedia multiplexing device and method using dynamic packet segmentation 156 1994
 
RAYTHEON COMPANY (1)
4719621 Packet fastbus 64 1985
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (6)
5257258 "Least time to reach bound" service policy for buffer systems 11 1991
5448708 System for asynchronously delivering enqueue and dequeue information in a pipe interface having distributed, shared memory 17 1992
5634015 Generic high bandwidth adapter providing data communications between diverse communication networks and computer system 132 1994
5671441 Method and apparatus for automatic generation of I/O configuration descriptions 87 1994
5715438 System and method for providing time base adjustment 28 1995
5768550 Bus interface logic system 15 1995
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
5668971 Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data transfer 118 1996
 
LSI LOGIC CORPORATION (1)
5210858 Clock division chip for computer system which interfaces a slower cache memory controller to be used with a faster processor 22 1989
 
LUCENT TECHNOLOGIES INC. (1)
4922486 User to network interface protocol for packet communications networks 338 1988
 
TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) (1)
5361252 Method and a device for monitoring channel split data packet transmission 17 1993
 
Dell USA, L.P. (1)
5657457 Method and apparatus for eliminating bus contention among multiple drivers without performance degradation 8 1994
 
LENOVO (SINGAPORE) PTE. LTD. (1)
5325492 System for asynchronously delivering self-describing control elements with a pipe interface having distributed, shared memory 64 1993
 
TERADATA US, INC. (1)
5764961 Predictable diverse data delivery enablement method and apparatus for ATM based computer system 25 1996
 
CONTEL FEDERAL SYSTEMS, INC., A DE CORP. (1)
4503499 Controlled work flow system 199 1982
 
MOTOROLA, INC. (1)
5751969 Apparatus and methods for predicting and managing congestion in a network 52 1995
 
ROUND ROCK RESEARCH, LLC (1)
* 6044474 Memory controller with buffered CAS/RAS external synchronization capability for reducing the effects of clock-to-signal skew 28 1997
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
5101347 System for reducing skew in the parallel transmission of multi-bit data slices 20 1988
 
XLNT Designs, Inc. (1)
5659718 Synchronous bus and bus interface device 83 1994
 
INTEL CORPORATION (10)
5404171 Method and apparatus for synchronizing digital packets of information to an arbitrary rate 17 1992
5471587 Fractional speed bus coupling 40 1992
5548733 Method and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus system 26 1994
5625779 Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge 41 1994
5894567 Mechanism for enabling multi-bit counter values to reliably cross between clocking domains 12 1995
5758166 Method and apparatus for selectively receiving write data within a write buffer of a host bridge 28 1996
5768545 Collect all transfers buffering mechanism utilizing passive release for a multiple bus environment 14 1996
5729760 System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode 132 1996
5784579 Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth 11 1996
* 6347351 Method and apparatus for supporting multi-clock propagation in a computer system having a point to point half duplex interconnect 15 1999
 
Amdahl Corporation (1)
5491799 Communication interface for uniform communication among hardware and software units of a computer system 17 1994
* Cited By Examiner

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