US Patent No: 7,016,989
Number of patents in Portfolio can not be more than 2000
Fast 16 bit, split transaction I/O bus
Stats
-
Mar 21, 2006
Issued date -
Dec 23, 1999
filing date -
09/471,445
serial no -
In Force
status
Importance
Loading Importance Indicators...
Abstract
A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of the reset signal such that the amount of logic required to latch and sample the data is minimized. As the timing budget is not limited to one clock cycle, devices can be spaced further apart providing more physical space for devices. Furthermore, skew sensitivity is reduced as to the skew is distributed over multiple clock periods.
Loading the Abstract Image...
First Claim
Related Publications
Loading Related Publications...
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
|
|
|||
| 5,404,171 Method and apparatus for synchronizing digital packets of information to an arbitrary rate | 17 | 1992 | |
| 5,471,587 Fractional speed bus coupling | 40 | 1992 | |
| 5,548,733 Method and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus system | 26 | 1994 | |
| 5,625,779 Arbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridge | 40 | 1994 | |
| 5,894,567 Mechanism for enabling multi-bit counter values to reliably cross between clocking domains | 9 | 1995 | |
| 5,758,166 Method and apparatus for selectively receiving write data within a write buffer of a host bridge | 24 | 1996 | |
| 5,768,545 Collect all transfers buffering mechanism utilizing passive release for a multiple bus environment | 14 | 1996 | |
| 5,729,760 System for providing first type access to register if processor in first mode and second type access to register if processor not in first mode | 122 | 1996 | |
| 5,784,579 Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth | 11 | 1996 | |
| 6,347,351 Method and apparatus for supporting multi-clock propagation in a computer system having a point to point half duplex interconnect | 13 | 1999 | |
|
|
|||
| 5,257,258 "Least time to reach bound" service policy for buffer systems | 11 | 1991 | |
| 5,448,708 System for asynchronously delivering enqueue and dequeue information in a pipe interface having distributed, shared memory | 14 | 1992 | |
| 5,634,015 Generic high bandwidth adapter providing data communications between diverse communication networks and computer system | 132 | 1994 | |
| 5,671,441 Method and apparatus for automatic generation of I/O configuration descriptions | 64 | 1994 | |
| 5,715,438 System and method for providing time base adjustment | 27 | 1995 | |
| 5,768,550 Bus interface logic system | 12 | 1995 | |
|
|
|||
| 5,802,278 Bridge/router architecture for high performance scalable networking | 206 | 1996 | |
| 5,668,971 Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data transfer | 108 | 1996 | |
| 5,862,338 Polling system that determines the status of network ports and that stores values indicative thereof | 92 | 1996 | |
|
|
|||
| 5,491,799 Communication interface for uniform communication among hardware and software units of a computer system | 17 | 1994 | |
|
|
|||
| 5,467,464 Adaptive clock skew and duty cycle compensation for a serial data bus | 62 | 1993 | |
|
|
|||
| 5,771,356 Apparatus for controlling FIFO buffer data transfer by monitoring bus status and FIFO buffer thresholds | 66 | 1995 | |
|
|
|||
| 4,503,499 Controlled work flow system | 188 | 1982 | |
|
|
|||
| 4,941,089 Input/output network for computer system | 147 | 1986 | |
|
|
|||
| 5,657,457 Method and apparatus for eliminating bus contention among multiple drivers without performance degradation | 8 | 1994 | |
|
|
|||
| 5,499,338 Bus system having a system bus, an internal bus with functional units coupled therebetween and a logic unit for use in such system | 11 | 1994 | |
|
|
|||
| 5,768,546 Method and apparatus for bi-directional transfer of data between two buses with different widths | 74 | 1996 | |
|
|
|||
| 6,330,650 Data receiver that performs synchronous data transfer with reference to memory module | 17 | 1998 | |
|
|
|||
| 5,325,492 System for asynchronously delivering self-describing control elements with a pipe interface having distributed, shared memory | 44 | 1993 | |
|
|
|||
| 5,210,858 Clock division chip for computer system which interfaces a slower cache memory controller to be used with a faster processor | 22 | 1989 | |
|
|
|||
| 4,922,486 User to network interface protocol for packet communications networks | 303 | 1988 | |
|
|
|||
| 5,905,766 Synchronizer, method and system for transferring data | 45 | 1996 | |
|
|
|||
| 5,541,919 Multimedia multiplexing device and method using dynamic packet segmentation | 132 | 1994 | |
|
|
|||
| 5,751,969 Apparatus and methods for predicting and managing congestion in a network | 45 | 1995 | |
|
|
|||
| 5,101,347 System for reducing skew in the parallel transmission of multi-bit data slices | 19 | 1988 | |
|
|
|||
| 5,574,862 Multiprocessing system with distributed input/output management | 39 | 1993 | |
|
|
|||
| 4,719,621 Packet fastbus | 61 | 1985 | |
|
|
|||
| 6,044,474 Memory controller with buffered CAS/RAS external synchronization capability for reducing the effects of clock-to-signal skew | 26 | 1997 | |
|
|
|||
| 5,361,252 Method and a device for monitoring channel split data packet transmission | 17 | 1993 | |
|
|
|||
| 5,764,961 Predictable diverse data delivery enablement method and apparatus for ATM based computer system | 22 | 1996 | |
|
|
|||
| 5,659,718 Synchronous bus and bus interface device | 73 | 1994 | |
|
|
|||
| 5,193,090 Access protection and priority control in distributed queueing | 34 | 1990 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Sep 21, 2013 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Sep 21, 2017 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 7.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |