Method of providing multiple logical bits per memory cell
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United States of America Patent
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Mar 28, 2006
Issued Date -
N/A
app pub date -
Jul 1, 2003
filing date -
Apr 9, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A semiconductor substrate is provided over which electrically conductive columns are formed along with electrically conductive rows crossing over the electrically conductive columns. A plurality of memory components are formed each having a resistance value corresponding to multiple logical bits and non-volatile memory cells are each formed by connecting a memory component between an electrically conductive row and an electrically conductive column.
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