Thermally enhanced semiconductor package
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United States of America Patent
Stats
-
Mar 28, 2006
Grant Date -
Dec 2, 2004
app pub date -
Aug 5, 2003
filing date -
May 28, 2003
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of the chip. An encapsulation body encapsulates the heat sink, chip and conductive bumps, while exposing a bottom or surfaces, not for attaching the chip, of the heat sink and ends of the conductive bumps outside. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with a plurality of openings for exposing predetermined portions of the conductive traces. A solder ball is implanted on each exposed portion of the conductive traces.
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