Multi-level semiconductor memory architecture and method of forming the same
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United States of America Patent
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Mar 28, 2006
Grant Date -
Feb 24, 2005
app pub date -
Oct 7, 2004
filing date -
Jul 5, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect routing channel through which a second group of local interconnect lines extend. The first group of local interconnect lines are configured to carry input information for accessing memory locations in which to store data or from which to retrieve data, and the second group of local interconnect lines are configured to carry a subset of the input information.
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