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Abstract

A clock data recovery (CDR) circuit that can be used for recovering data from a high-speed serial transmission using components that operate at a fraction of the data speed. The CDR consists of a phase detector, an averaging circuit and a phase interpolator. The phase detector samples each data bit at its midpoint and at its transitional region and then compares the two samples to determine whether the sampling clock, which is generated by a phase interpolator, is leading or lagging the data stream. The averaging circuit filters out the high frequency jitters in the phase detector output and then passes the filtered signals on to the phase interpolator for phase selection. The phase interpolator uses the filtered signals from the averaging circuit as a guide in the selection of an output clock phase that minimizes the phase difference between the output clock and the incoming data.

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First Claim