Reduced power option
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United States of America Patent
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Mar 28, 2006
Issued Date -
N/A
app pub date -
Jun 1, 2001
filing date -
Jun 1, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one processor cycle and with one power mode instruction employing clock transition logic within the processor to initiate a switch to the clock source configuration specified by a literal, such as a 3-bit literal. Operand may be written the register of clock transition logic to define an exit state for a sleep mode.
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