Method for monitoring and improving integrated circuit fabrication using FPGAs
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United States of America Patent
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Mar 28, 2006
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app pub date -
Mar 24, 2004
filing date -
Mar 24, 2004
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Abstract
Methods for monitoring and improving the fabrication process of integrated circuits using configurable devices are described. In one aspect, the method includes instantiating a test pattern on one or more configurable devices fabricated using the fabrication process, identifying an underperforming region of the configurable devices, and determining if the underperforming region is layout sensitive. At least one of the fabrication process and the layout of the configurable device can then be adjusted based on the determination. In some embodiments, the configurable device may be a programmable logic device, such as a field programmable logic array.
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