Method and apparatus for decomposing a region of an integrated circuit layout
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United States of America Patent
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Mar 28, 2006
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app pub date -
Aug 28, 2002
filing date -
Jan 22, 2002
priority date (Note) -
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Abstract
Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit ('IC') layout. The method defines several nodes in the region. The method then specifies a plurality of edges in the region. Each edge is between a pair of nodes, and some edges are neither perpendicular nor parallel to some of the edges. The method uses the edges to define routes in the region.
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