Architecture for synchronizing and resetting clock signals supplied to multiple programmable analog blocks
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United States of America Patent
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Apr 4, 2006
Grant Date -
N/A
app pub date -
Oct 1, 2001
filing date -
Oct 26, 2000
priority date (Note) -
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Abstract
A circuit for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. The circuit is coupled to the analog blocks to supply a synchronized clock signal to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The circuit allows the frequency of the clock signal to be changed dynamically depending on the analog function to be achieved. The circuit also establishes phase alignment when a frequency change occurs.
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