Low profile chip scale stacking system and method
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United States of America Patent
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Apr 11, 2006
Issued Date -
N/A
app pub date -
Jul 11, 2003
filing date -
Oct 26, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile contacts are created by any of a variety of methods and materials. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry that exhibit one or two or more conductive layers.
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