Power semiconductor component in the planar technique
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Apr 18, 2006
Issued Date -
N/A
app pub date -
Mar 14, 2005
filing date -
Mar 16, 2004
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In a power semiconductor component produced in a planar technique, a near-surface structure having at least one depression is formed in a surface region of an edge termination adjacent a main surface of the semiconductor body. The structure lies inside a space charge region formed when a voltage is applied at a junction between semiconductor regions of opposite conduction type. Dielectric material may fill the depression and form a passivation layer on the surface region. The depression may be an annular trench having a width to depth ratio ≦1. Alternatively, the structure may be waffle-shaped with multiple depressions.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully