Method and apparatus for decomposing a region of an integrated circuit layout
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United States of America Patent
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Apr 18, 2006
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N/A
app pub date -
Aug 28, 2002
filing date -
Jan 22, 2002
priority date (Note) -
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Abstract
Some embodiments of the invention provide a method of decomposing a region of an intergrated circuit ('IC') layout. The region contains several routable elements. Based on the routable elements, the method defines a plurality of nodes in the region. It then triangulates the region based on the nodes. The method then uses the triangles to define routes in the region.
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