Importance

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Abstract

Opportunities to transmit ATM cells of identical level onto an ATM line are equally afforded to respective terminal side lines. In a cell assembler/disassembler, data from the terminal side lines 1100 are turned into ATM cells, and the ATM cells are assigned priority levels. Then, the ATM cells are stored in internal buffers 111-116 respectively corresponding to the terminal side lines 1100. The priority controller 1210 selects the ATM cells of the highest priority levels from within the respective internal buffers, and further selects the ATM cell of the highest priority level as an ATM cell to-be-transmitted from among the selected ATM cells. In the presence of a plurality of such ATM cells of the highest priority level, the priority controller 1210 determines the ATM cell to-be-transmitted in accordance with the priority sequence of the internal buffers in which the ATM cells of the highest priority level are stored. Each time the priority controller 1210 selects the ATM cell to-be-transmitted, it alters the priority sequence of the internal buffers so that the priority sequence of the internal buffer having stored the ATM cell to-be-transmitted therein may become the latest.

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First Claim