US Patent No: 7,036,105

Number of patents in Portfolio can not be more than 2000

Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's

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Abstract

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Some embodiments of the invention provide an integrated-circuit chip that has a design based on a wiring model that allows at least a particular wiring layer to have more than one preferred wiring directions. Other embodiments provide a method of manufacturing an integrated circuit ('IC') that has a plurality of wiring layers. The method specifies a layout of the IC by using a wiring model that specifies more than one preferred wiring direction for at least a region of a particular wiring layer. The method then uses the layout to fabricate the integrated circuit.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
CADENCE DESIGN SYSTEMS, INC.SAN JOSE, CA1579

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Caldwell, Andrew Santa Clara, CA 110 957
Jacques, Etienne Bristol, GB 47 384
Teig, Steven Menlo Park, CA 466 4352

Cited Art Landscape

Patent Info (Count) # Cites Year
 
LSI LOGIC CORPORATION (31)
5,914,887 Congestion based cost factor computing apparatus for integrated circuit physical design automation system 115 1994
6,155,725 Cell placement representation and transposition for integrated circuit physical design automation system 115 1994
5,578,840 Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometry 139 1994
5,532,934 Floorplanning technique using multi-partitioning based on a partition cost factor for non-square shaped partitions 98 1995
5,742,086 Hexagonal DRAM array 98 1995
5,777,360 Hexagonal field programmable gate array architecture 244 1995
5,811,863 Transistors having dynamically adjustable characteristics 139 1995
5,822,214 CAD for hexagonal architecture 203 1995
5,889,329 Tri-directional interconnect architecture for SRAM 94 1995
5,973,376 Architecture having diamond shaped or parallelogram shaped cells 114 1995
6,407,434 Hexagonal architecture 126 1995
5,637,920 High contact density ball grid array package for flip-chips 251 1995
5,636,125 Computer implemented method for producing optimized cell placement for integrated circiut chip 141 1995
5,650,653 Microelectronic integrated circuit including triangular CMOS "nand" gate device 122 1995
6,216,252 Method and system for creating, validating, and scaling structural description of electronic device 193 1996
5,980,093 Integrated circuit layout routing using multiprocessing 167 1996
5,898,597 Integrated circuit floor plan optimization system 101 1997
6,067,409 Advanced modular cell placement system 112 1997
6,058,254 Method and apparatus for vertical congestion removal 85 1997
6,068,662 Method and apparatus for congestion removal 93 1997
6,123,736 Method and apparatus for horizontal congestion removal 86 1997
6,154,874 Memory-saving method and apparatus for partitioning high fanout nets 62 1998
6,175,950 Method and apparatus for hierarchical global routing descend 112 1998
6,230,306 Method and apparatus for minimization of process defects while routing 108 1998
6,247,167 Method and apparatus for parallel Steiner tree routing 99 1998
6,253,363 Net routing using basis element decomposition 111 1998
6,289,495 Method and apparatus for local optimization of the global routing 117 1998
6,324,674 Method and apparatus for parallel simultaneous global and detail routing 147 1998
6,088,519 Method and system for improving a placement of cells using energetic placement with alternating contraction and expansion operations 75 1998
6,412,102 Wire routing optimization 103 1998
6,473,891 Wire routing to control skew 79 2000
 
CADENCE DESIGN SYSTEMS, INC. (11)
5,663,891 Optimization of multiple performance criteria of integrated circuits by expanding a constraint graph with subgraphs derived from multiple PWL convex cost functions 104 1996
5,838,583 Optimized placement and routing of datapaths 211 1996
6,543,043 Inter-region constraint-based router for use in electronic design automation 112 2000
6,858,928 Multi-directional wiring on a single metal layer 18 2000
6,711,727 Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits 51 2001
6,526,555 Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction 68 2001
6,769,105 Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits 16 2001
6,858,935 Simulating euclidean wiring directions using manhattan and diagonal directional wires 11 2002
6,859,916 Polygonal vias 14 2002
6,829,757 Method and apparatus for generating multi-layer routes 22 2002
6,848,091 Partitioning placement method and apparatus 8 2002
 
KABUSHIKI KAISHA TOSHIBA (10)
5,224,057 Arrangement method for logic cells in semiconductor IC device 218 1992
5,723,908 Multilayer wiring structure 199 1994
5,634,093 Method and CAD system for designing wiring patterns using predetermined rules 93 1995
5,633,479 Multilayer wiring structure for attaining high-speed signal propagation 123 1995
5,635,736 MOS gate type semiconductor device 106 1995
6,110,222 Layout design method and system for an improved place and route 47 1998
6,262,487 Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method 293 1999
6,546,540 Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program 105 2000
6,436,804 Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method 107 2001
6,645,842 Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method 96 2002
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (9)
4,615,011 Iterative method for establishing connections and resulting product 233 1983
4,782,193 Polygonal wiring for improved package performance 110 1987
5,880,969 Method and apparatus for deciding a wiring route and for detecting a critical cut 78 1996
6,226,560 Method and apparatus for optimizing the path of a physical wire 100 1998
6,247,853 Incremental method for critical area and critical region computation of via blocks 71 1998
6,219,823 Method and apparatus for deciding a wiring route and for detecting a critical cut 79 1998
6,295,634 Wiring design apparatus, wiring determination apparatus and methods thereof 101 1999
6,401,234 Method and system for re-routing interconnects within an integrated circuit design having blockages and bays 90 1999
6,490,713 Method and apparatus for automatically generating multi-terminal nets, and program storage medium storing program for executing automatic multi-terminal net generation method 109 2001
 
FUJITSU LIMITED (5)
5,889,677 Circuit designing apparatus of an interactive type 139 1995
6,111,756 Universal multichip interconnect systems 105 1998
6,327,694 Cell placement apparatus and method, and computer readable record medium having cell placement program recorded thereon 94 1998
6,316,838 Semiconductor device 320 2000
6,415,427 Method and apparatus for global routing, and storage medium having global routing program stored therein 57 2001
 
SYNOPSYS, INC. (5)
6,286,128 Method for design optimization using logical and physical information 139 1998
6,324,675 Efficient iterative, gridless, cost-based fine router for computer controlled integrated circuit design 152 1998
6,349,403 Interative, gridless, cost-based layer assignment coarse router for computer controlled IC design 122 1998
6,557,145 Method for design optimization using logical and physical information 156 2001
6,567,967 Method for designing large standard-cell base integrated circuits 105 2001
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (4)
5,877,091 Multilayer routing method and structure for semiconductor integrated circuit 52 1996
6,330,707 Automatic routing method 109 1998
6,434,730 Pattern forming method 49 2000
6,609,237 Routing path finding method for automated routing/designing process and computer-readable storage medium having stored thereon routing path finding program 50 2000
 
FREESCALE SEMICONDUCTOR, INC. (3)
6,505,331 Method for routing of nets in an electronic device 58 1996
6,006,024 Method of routing an integrated circuit 100 1996
6,209,123 Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors 351 1996
 
INTEL CORPORATION (3)
6,166,441 Method of forming a via overlap 53 1998
6,442,745 Method and apparatus for layout-constrained global routing 74 1999
6,519,751 Method and apparatus for accurate crosspoint allocation in VLSI area routing 76 2000
 
MITSUBISHI DENKI KABUSHIKI KAISHA (3)
4,673,966 Semiconductor integrated circuit 110 1984
5,859,449 Semiconductor integrated circuit 79 1997
6,463,575 Cell-layout method in integrated circuit devices 75 2000
 
NEC ELECTRONICS CORPORATION (3)
5,717,600 Method for designing an interconnection route in an LSI 55 1996
6,378,121 Automatic global routing device for efficiently determining optimum wiring route on integrated circuit and global routing method therefor 84 1998
6,154,873 Layout designing method and layout designing apparatus 51 1998
 
SUN MICROSYSTEMS, INC. (3)
2002/0104,061 Systems and methods for linear minimal convolution 49 2001
2003/0009,737 Detailed method for routing connections using tile expansion techniques and associated methods for designing and manufacturing VLSI circuits 46 2002
2004/0044,979 Constraint-based global router for routing high performance designs 89 2002
 
MENTOR GRAPHICS CORPORATION (2)
5,757,656 Method for routing breakouts 118 1995
6,327,693 Interconnect delay driven placement and routing of an integrated circuit design 104 1999
 
NEC CORPORATION (2)
4,855,929 Routing method for use in wiring design 108 1987
5,757,089 Method of automatic wiring 116 1995
 
NEC TOPPAN CIRCLE SOLUTIONS, INC. (2)
6,035,108 Figure layout compaction method and compaction device 98 1997
6,301,686 Graphic layout compaction system capable of compacting a layout at once 137 1999
 
NEC TOPPAN CIRCUIT SOLUTIONS, INC. (2)
6,385,758 System and method for compacting a graphic layout 120 1999
6,412,097 COMPACTING METHOD OF CIRCUIT LAYOUT BY MOVING COMPONENTS USING MARGINS AND BUNDLE WIDTHS IN COMPLIANCE WITH THE DESIGN RULE, A DEVICE USING THE METHOD AND A COMPUTER PRODUCT ENABLING PROCESSOR TO PERFORM THE METHOD 119 2000
 
RENESAS ELECTRONICS CORPORATION (2)
5,375,069 Wiring routes in a plurality of wiring layers 139 1994
6,656,644 Manufacturing method of photomask and photomask 51 2001
 
XILINX, INC. (2)
5,659,484 Frequency driven layout and method for field programmable gate arrays 220 1995
6,601,227 Method for making large-scale ASIC using pre-engineered long distance routing structure 250 2001
 
AMKOR TECHNOLOGY, INC. (1)
6,150,193 RF shielded device 144 1998
 
APACK TECHNOLOGIES INC. (1)
6,307,256 Semiconductor package with a stacked chip on a leadframe 81 1998
 
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (1)
6,405,358 Method for estimating and displaying wiring congestion 89 1999
 
BSC ACQUISTION, INC. (1)
6,260,179 Cell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program 165 1998
 
DEUTSCHE BANK AG NEW YORK BRANCH (1)
2001/0003,843 ADVANCED MODULAR CELL PLACEMENT SYSTEM 3 1999
 
FormFactor, Inc. (1)
2004/0088,670 Process and apparatus for finding paths through a routing space 48 2003
 
Fujitsu VLSI Limited (1)
5,618,744 Manufacturing method and apparatus of a semiconductor integrated circuit device 107 1993
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
6,219,832 System and method of using annotations to optimize dynamically translated code in the presence of signals 70 1998
 
HITACHI, LTD. (1)
5,657,242 Method of determining routes for a plurality of wiring connections and a circuit board produced by such a method 109 1993
 
LUCENT TECHNOLOGIES INC. (1)
6,586,281 Variable rotational assignment of interconnect levels in integrated circuit fabrication 36 2000
 
MICRON TECHNOLOGY, INC. (1)
6,448,591 Metallization line layout 96 1999
 
NORTEL NETWORKS LIMITED (1)
4,777,606 Method for deriving an interconnection route between elements in an interconnection medium 146 1986
 
ROUTECH, INC. (1)
2001/0038,612 Automatic routing system for circuit layout 56 2001
 
TEXAS INSTRUMENTS INCORPORATED (1)
6,038,383 Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability 77 1997
 
TRANSPACIFIC DIGITAL SYSTEMS, LLC (1)
5,360,948 Via programming for multichip modules 74 1992
 
VLSI TECHNOLOGY, INC. (1)
5,856,927 Method for automatically routing circuits of very large scale integration (VLSI) 76 1995
 
Other [Check patent profile for assignment information] (1)
6,128,767 Polygon representation in an integrated circuit layout 109 1997

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
CADENCE DESIGN SYSTEMS, INC. (9)
7,707,537 Method and apparatus for generating layout regions with local preferred directions 2 2004
7,441,220 Local preferred direction architecture, tools, and apparatus 9 2004
7,412,682 Local preferred direction routing 5 2004
7,340,711 Method and apparatus for local preferred direction routing 10 2004
8,201,128 Method and apparatus for approximating diagonal lines in placement 1 2006
7,594,196 Block interstitching using local preferred direction architectures, tools, and apparatus 0 2006
8,250,514 Localized routing direction 2 2006
8,166,442 Local preferred direction architecture 0 2008
8,010,929 Method and apparatus for generating layout regions with local preferred directions 3 2010
 
INNOVATIONAL HOLDINGS LLC (1)
8,365,122 Method and apparatus for configurable systems 0 2011

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