Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7036105
SERIAL NO

10229311

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Some embodiments of the invention provide an integrated-circuit chip that has a design based on a wiring model that allows at least a particular wiring layer to have more than one preferred wiring directions. Other embodiments provide a method of manufacturing an integrated circuit ('IC') that has a plurality of wiring layers. The method specifies a layout of the IC by using a wiring model that specifies more than one preferred wiring direction for at least a region of a particular wiring layer. The method then uses the layout to fabricate the integrated circuit.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
Cadence Design Systems, Inc.SAN JOSE, CA1739

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Caldwell, Andrew Santa Clara, CA 107 1223
Jacques, Etienne Bristol, GB 32 532
Teig, Steven Menlo Park, CA 326 5441

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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Other [Check patent profile for assignment information] (1)
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HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP (1)
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Cadence Design Systems, Inc. (11)
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5838583 Optimized placement and routing of datapaths 223 1996
6543043 Inter-region constraint-based router for use in electronic design automation 116 2000
* 6858928 Multi-directional wiring on a single metal layer 19 2000
* 6711727 Method and arrangement for layout and manufacture of gridless nonManhattan semiconductor integrated circuits 55 2001
* 6526555 Method for layout and manufacture of gridless non manhattan semiconductor integrated circuits using compaction 72 2001
* 6769105 Method and arrangement for layout and manufacture of gridded non manhattan semiconductor integrated circuits 27 2001
* 6858935 Simulating euclidean wiring directions using manhattan and diagonal directional wires 12 2002
* 6859916 Polygonal vias 15 2002
* 6829757 Method and apparatus for generating multi-layer routes 23 2002
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KABUSHIKI KAISHA TOSHIBA (10)
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5578840 Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometry 144 1994
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5811863 Transistors having dynamically adjustable characteristics 145 1995
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5889329 Tri-directional interconnect architecture for SRAM 98 1995
5973376 Architecture having diamond shaped or parallelogram shaped cells 121 1995
6407434 Hexagonal architecture 151 1995
5637920 High contact density ball grid array package for flip-chips 257 1995
5980093 Integrated circuit layout routing using multiprocessing 179 1996
5898597 Integrated circuit floor plan optimization system 101 1997
6058254 Method and apparatus for vertical congestion removal 85 1997
6068662 Method and apparatus for congestion removal 93 1997
6123736 Method and apparatus for horizontal congestion removal 86 1997
6154874 Memory-saving method and apparatus for partitioning high fanout nets 65 1998
6175950 Method and apparatus for hierarchical global routing descend 117 1998
6230306 Method and apparatus for minimization of process defects while routing 112 1998
6247167 Method and apparatus for parallel Steiner tree routing 99 1998
6253363 Net routing using basis element decomposition 116 1998
6289495 Method and apparatus for local optimization of the global routing 121 1998
6324674 Method and apparatus for parallel simultaneous global and detail routing 152 1998
6412102 Wire routing optimization 105 1998
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6473891 Wire routing to control skew 85 2000
 
NEC ELECTRONICS CORPORATION (3)
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INTERNATIONAL BUSINESS MACHINES CORPORATION (8)
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FUJITSU LIMITED (5)
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INTEL CORPORATION (3)
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TEXAS INSTRUMENTS INCORPORATED (1)
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MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (3)
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NORTEL NETWORKS LIMITED (1)
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* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
* 2009/0024,977 LOCAL PREFERRED DIRECTION ARCHITECTURE, TOOLS, AND APPARATUS 6 2008
 
LIZOTECH, INC. (1)
* 2007/0174,803 Method for concurrent search and select of routing patterns for a routing system 1 2007
 
Cadence Design Systems, Inc. (15)
7707537 Method and apparatus for generating layout regions with local preferred directions 2 2004
7441220 Local preferred direction architecture, tools, and apparatus 9 2004
7412682 Local preferred direction routing 7 2004
* 7340711 Method and apparatus for local preferred direction routing 13 2004
* 2005/0273,746 Method and apparatus for generating layout regions with local preferred directions 13 2004
* 2005/0273,747 Local preferred direction routing 2 2004
* 2005/0273,748 Local preferred direction routing 2 2004
* 2005/0229,134 Local preferred direction architecture, tools, and apparatus 6 2004
* 2005/0240,893 Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated euclidean wiring 22 2005
8201128 Method and apparatus for approximating diagonal lines in placement 1 2006
7594196 Block interstitching using local preferred direction architectures, tools, and apparatus 1 2006
* 2006/0248,492 Block interstitching using local preferred direction architectures, tools, and apparatus 5 2006
8250514 Localized routing direction 5 2006
8166442 Local preferred direction architecture 1 2008
8010929 Method and apparatus for generating layout regions with local preferred directions 5 2010
 
INNOVATIONAL HOLDINGS LLC (1)
8365122 Method and apparatus for configurable systems 0 2011
* Cited By Examiner

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