Method of manufacturing spacers on sidewalls of titanium polycide gate

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United States of America Patent

PATENT NO 7037796
SERIAL NO

09598673

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Abstract

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Disclosed is a method for manufacturing a semiconductor device, more particularly to a method of forming a spacer on side-walls of a titanium polycide gate. The method for manufacturing the semiconductor device is as follows. There is provided a semiconductor substrate in which a gate oxide layer, a polysilicon layer, a titanium silicide layer and a patterned hard mask layer are sequentially formed. Herein, the titanium polycide gate is fabricated by an etching step employing the patterned hard mask. Afterward, the substrate is thermal-treated at temperature of 700.about.750.degree. C. according to a gate re-oxidation process, thereby forming a re-oxidation layer on side-walls of the gate and on the substrate surface. Next, an oxide layer for spacer is deposited on the resultant at process temperature of 350.about.750 C., and a nitride layer is deposited on the oxide layer. Thereafter, a spacer is formed on side-walls of the gate and the hard mask layer by blanket-etching the nitride layer, the oxide layer and the re-oxidation layer.

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Patent Owner(s)

Patent OwnerAddress
INTELLECTUAL DISCOVERY CO LTD15TH FLOOR MAIN BUILDING 433 SEOLLEUNG-RO GANGNAM-GU SEOUL 06212 06212

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jang, Se Aug Kyoungki-do, KR 48 543
Kim, Tae Kyun Kyoungki-do, KR 116 1196

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