Read approach for multi-level virtual ground memory
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United States of America Patent
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May 2, 2006
Grant Date -
Mar 23, 2006
app pub date -
Sep 22, 2004
filing date -
Sep 22, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention pertains to a technique for determining the level of a bit in a dual sided ONO flash memory cell where each of the bits of the dual sided ONO flash memory cell can be programmed to multiple levels. One or more aspects of the present invention take into consideration the affect that the level of charge on one bit can have on the other bit, otherwise known as complimentary bit disturb. A metric known as transconductance is utilized in making the bit level determination to provide a greater degree of resolution and accuracy. In this manner, determining the bit level in accordance with one or more aspects of the present invention mitigates false or erroneous reads.
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