Block RAM with embedded FIFO buffer
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United States of America Patent
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May 2, 2006
Grant Date -
N/A
app pub date -
May 4, 2004
filing date -
May 4, 2004
priority date (Note) -
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Abstract
A programmable logic device includes a block random access memory ('BRAM') with an embedded first in, first out ('FIFO') controller. Embedding the FIFO logic in silicon, rather than configuring it in the fabric of the programmable logic device, provides a reliable, high-speed asynchronous FIFO memory system.
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