Content addressable memory with priority-biased error detection sequencing
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United States of America Patent
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May 9, 2006
Issued Date -
N/A
app pub date -
Nov 1, 2001
filing date -
Aug 3, 2001
priority date (Note) -
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Abstract
A content addressable memory (CAM) device having circuitry to generate a biased sequence of addresses. A first counter circuit increments an address value in response to a clock signal and resets the address value to a start address in response to a control signal. A second counter increments a limit value in response to a control signal. A compare circuit compares the address value and the limit value and, if the address value and the limit value have a predetermined relationship, asserts the control signal.
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