Use of voids between elements in semiconductor structures for isolation
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United States of America Patent
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May 16, 2006
Grant Date -
Nov 25, 2004
app pub date -
May 21, 2003
filing date -
May 21, 2003
priority date (Note) -
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Abstract
A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage elements and resulting errors occurring in the data read from the array.
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