Semiconductor device and manufacturing method thereof

United States of America Patent

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May 16, 2006
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Nov 6, 2003
app pub date
May 16, 2003
filing date
Dec 25, 1998

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Abstract

There is presented a structure in which outlines of a metal interconnection 111 that is laid in an interlayer insulating film are covered with a barrier metal film 110. As the material for the barrier metal film 110, TaN or the like is utilized.

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Patent Owner	Address
TESSERA ADVANCED TECHNOLOGIES INC	3025 ORCHARD PARKWAY SAN JOSE CA 95134

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H01L:SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICE....

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Inventor Name	Address	# of filed Patents	Total Citations
Usami, Tatsuya	Tokyo, JP	140	2299

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Semiconductor device and manufacturing method thereof

Number of patents in Portfolio can not be more than 2000

United States of America Patent

10438887

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PATENT NO	7045898
APP PUB NO	20030205810A1
SERIAL NO	10438887
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
May 16, 2006	US,7045898,B2 US7045898B2	GRANTED PATENT AS SECOND PUBLICATION
November 06, 2003	US,20030205810,A1 US20030205810A1	FIRST PUBLISHED PATENT APPLICATION

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10438887

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