US Patent No: 7,046,568

Number of patents in Portfolio can not be more than 2000

Memory sensing circuit and method for low voltage operation

1 Status Updates

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A sensing module operates with a sense amplifier sensing a conduction current of a memory cell via a coupled bit line under constant voltage condition in order to minimize bit-line to bit-line coupling. The rate of discharge of a dedicated capacitor as measured by a change in the voltage drop there across in a predetermined period is used to indicate the magnitude of the conduction current. The voltage cannot drop below a minimum level imposed by a circuit for maintaining the constant voltage condition on the bit line. A voltage shifter is used to boost the voltage during the discharge and to unboost the voltage after the discharge, so that the change in voltage drop properly reflects the rate of discharge without running into the minimum level.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
SANDISK TECHNOLOGIES LLCPLANO, TX3430

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cernea, Raul-Adrian Santa Clara, CA 126 5303

Cited Art Landscape

Patent Info (Count) # Cites Year
 
SHARP KABUSHIKI KAISHA (1)
6,744,667 BIT LINE CONTROL DECODER CIRCUIT, VIRTUAL GROUND TYPE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE PROVIDED WITH THE DECODER CIRCUIT, AND DATA READ METHOD OF VIRTUAL GROUND TYPE NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 54 2002
 
CYPRESS SEMICONDUCTOR CORPORATION (1)
4,785,427 Differential bit line clamp 71 1987
 
SONY CORPORATION (1)
5,920,502 Nonvolatile semiconductor memory with fast data programming and erasing function using ECC 63 1997
 
SAMSUNG ELECTRONICS CO., LTD. (2)
6,490,199 Sense amplifier circuit for a flash memory device 72 2001
6,731,539 Memory with offset bank select cells at opposite ends of buried diffusion lines 44 2003
 
FUJITSU LIMITED (1)
5,537,356 Nonvolatile semiconductor memory 49 1995
 
SANDISK TECHNOLOGIES LLC (9)
5,095,344 Highly compact EPROM and flash EEPROM devices 746 1988
5,070,032 Method of making dense flash EEprom semiconductor memory structures 529 1989
5,172,338 Multi-state EEprom read and write circuits and techniques 1129 1990
5,343,063 Dense vertical programmable read only memory cell structure and processes for making them 487 1990
5,315,541 Segmented column memory array 735 1992
5,661,053 Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers 460 1994
5,595,924 Technique of forming over an irregular surface a polysilicon layer with a smooth surface 255 1994
6,222,762 Multi-state memory 901 1997
6,407,953 Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays 153 2001
 
VALLEY DEVICE MANAGEMENT (1)
6,504,757 Double boosting scheme for NAND to improve program inhibit characteristics 62 2001
 
SGS-Ates Componenti Elettronici S.P.A. (1)
4,357,685 Method of programming an electrically alterable nonvolatile memory 217 1980
 
TEXAS INSTRUMENTS INCORPORATED (1)
5,093,806 Sensing and decoding scheme for a BiCMOS read/write memory 70 1989
 
KABUSHIKI KAISHA TOSHIBA (10)
5,418,752 Flash EEPROM system with erase sector select 420 1992
5,570,315 Multi-state EEPROM having write-verify control circuit 847 1994
* 5,650,970 semiconductor memory device having a flash write function 32 1995
5,774,397 Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state 548 1996
5,903,495 Semiconductor device and memory system 381 1997
6,097,638 Semiconductor memory device 94 1998
6,011,287 Non-volatile semiconductor memory device 120 1998
6,046,935 Semiconductor device and memory system 823 1999
6,046,940 Nonvolatile semiconductor memory device 80 1999
6,373,746 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells 238 2000
 
SAIFUN SEMICONDUCTORS LTD. (2)
5,768,192 Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping 908 1996
6,011,725 Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping 1125 1999
 
STMICROELECTRONICS, INC. (1)
5,949,720 Voltage clamping method and apparatus for dynamic random access memory devices 48 1998
 
NEC ELECTRONICS CORPORATION (1)
5,245,571 Sense amplifier circuit implemented by bipolar transistor and improved in current consumption 49 1991
 
Radiant Technologies, Inc. (1)
5,872,739 Sense amplifier for low read-voltage memory cells 59 1997
 
Datalight, Incorporated (1)
5,860,082 Method and apparatus for allocating storage in a flash memory 103 1996
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
* 2007/0277,528 PREMIXING INJECTOR FOR GAS TURBINE ENGINES 2 2007
 
SANDISK TECHNOLOGIES LLC (201)
7,443,757 Non-volatile memory and method with reduced bit line crosstalk errors 8 2002
* 2004/0057,318 Non-volatile memory and method with reduced bit line crosstalk errors 9 2002
7,251,160 Non-volatile memory and method with power-saving read and program-verify operations 41 2005
* 2006/0209,592 Non-volatile memory and method with power-saving read and program-verify operations 4 2005
7,366,022 Apparatus for programming of multi-state non-volatile memory using smart verify 14 2005
7,301,817 Method for programming of multi-state non-volatile memory using smart verify 99 2005
* 2007/0097,747 Apparatus for programming of multi-state non-volatile memory using smart verify 2 2005
* 2007/0097,749 Method for programming of multi-state non-volatile memory using smart verify 4 2005
7,355,888 Apparatus for programming non-volatile memory with reduced program disturb using modified pass voltages 14 2005
7,355,889 Method for programming non-volatile memory with reduced program disturb using modified pass voltages 31 2005
* 2007/0171,719 Method for programming non-volatile memory with reduced program disturb using modified pass voltages 14 2005
* 2007/0171,718 Apparatus for programming non-volatile memory with reduced program disturb using modified pass voltages 0 2005
7,327,619 Reference sense amplifier for non-volatile memory 8 2005
7,324,393 Method for compensated sensing in non-volatile memory 37 2005
* 2006/0158,947 Reference sense amplifier for non-volatile memory 8 2005
* 2006/0158,935 Method for compensated sensing in non-volatile memory 3 2005
7,310,255 Non-volatile memory with improved program-verify operations 85 2005
* 2007/0171,725 Non-volatile memory with improved program-verify operations 1 2005
* 7,224,614 Methods for improved program-verify operations in non-volatile memories 38 2005
7,619,922 Method for non-volatile memory with background data latch caching during erase operations 41 2006
7,609,552 Non-volatile memory with background data latch caching during erase operations 1 2006
7,505,320 Non-volatile memory with background data latch caching during program operations 19 2006
7,502,260 Method for non-volatile memory with background data latch caching during program operations 19 2006
7,486,558 Non-volatile memory with managed execution of cached data 6 2006
7,480,181 Non-volatile memory with background data latch caching during read operations 12 2006
7,463,521 Method for non-volatile memory with managed execution of cached data 38 2006
7,447,078 Method for non-volatile memory with background data latch caching during read operations 22 2006
* 2006/0233,022 Non-Volatile Memory with Background Data Latch Caching During Program Operations 21 2006
* 2006/0233,021 Non-Volatile Memory with Background Data Latch Caching During Erase Operations 19 2006
* 2006/0233,023 Method for Non-Volatile Memory with Background Data Latch Caching During Erase Operations 39 2006
* 2006/0221,696 Method for Non-Volatile Memory with Background Data Latch Caching During Read Operations 11 2006
7,376,030 Memory sensing circuit and method for low voltage operation 12 2006
7,391,650 Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates 16 2006
7,342,831 System for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates 91 2006
* 2007/0291,566 METHOD FOR OPERATING NON-VOLATILE MEMORY USING TEMPERATURE COMPENSATION OF VOLTAGES OF UNSELECTED WORD LINES AND SELECT GATES 5 2006
7,492,633 System for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines 4 2006
7,349,261 Method for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines 7 2006
* 2007/0291,543 METHOD FOR INCREASING PROGRAMMING SPEED FOR NON-VOLATILE MEMORY BY APPLYING COUNTER-TRANSITIONING WAVEFORMS TO WORD LINES 3 2006
7,489,549 System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages 22 2006
7,486,561 Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages 10 2006
* 2007/0297,245 SYSTEM FOR NON-REAL TIME REPROGRAMMING OF NON-VOLATILE MEMORY TO ACHIEVE TIGHTER DISTRIBUTION OF THRESHOLD VOLTAGES 10 2006
* 2007/0297,226 METHOD FOR NON-REAL TIME REPROGRAMMING OF NON-VOLATILE MEMORY TO ACHIEVE TIGHTER DISTRIBUTION OF THRESHOLD VOLTAGES 41 2006
7,957,185 Non-volatile memory and method with power-saving read and program-verify operations 4 2006
7,570,513 Non-volatile memory and method with power-saving read and program-verify operations 9 2006
* 2007/0014,161 Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations 13 2006
* 2007/0014,156 Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations 2 2006
7,977,186 Providing local boosting control implant for non-volatile memory 1 2006
7,705,387 Non-volatile memory with local boosting control implant 3 2006
* 2008/0081,419 PROVIDING LOCAL BOOSTING CONTROL IMPLANT FOR NON-VOLATILE MEMORY 4 2006
* 2008/0079,052 NON-VOLATILE MEMORY WITH LOCAL BOOSTING CONTROL IMPLANT 3 2006
7,691,710 Fabricating non-volatile memory with dual voltage select gate structure 7 2006
7,616,490 Programming non-volatile memory with dual voltage select gate structure 10 2006
7,586,157 Non-volatile memory with dual voltage select gate structure 4 2006
* 2008/0089,128 PROGRAMMING NON-VOLATILE MEMORY WITH DUAL VOLTAGE SELECT GATE STRUCTURE 1 2006
* 2008/0090,351 FABRICATING NON-VOLATILE MEMORY WITH DUAL VOLTAGE SELECT GATE STRUCTURE 2 2006
* 2008/0089,127 NON-VOLATILE MEMORY WITH DUAL VOLTAGE SELECT GATE STRUCTURE 19 2006
7,468,911 Non-volatile memory using multiple boosting modes for reduced program disturb 80 2006
7,440,323 Reducing program disturb in non-volatile memory using multiple boosting modes 15 2006
* 2008/0123,426 NON-VOLATILE MEMORY USING MULTIPLE BOOSTING MODES FOR REDUCED PROGRAM DISTURB 30 2006
* 2008/0123,425 REDUCING PROGRAM DISTURB IN NON-VOLATILE MEMORY USING MULTIPLE BOOSTING MODES 5 2006
7,696,035 Method for fabricating non-volatile memory with boost structures 3 2006
7,508,710 Operating non-volatile memory with boost structures 77 2006
7,508,703 Non-volatile memory with boost structures 3 2006
* 2008/0112,226 NON-VOLATILE MEMORY WITH BOOST STRUCTURES 23 2006
* 2008/0113,479 FABRICATING NON-VOLATILE MEMORY WITH BOOST STRUCTURES 6 2006
7,508,721 Use of data latches in multi-phase programming of non-volatile memories 26 2006
* 2007/0097,744 Use of Data Latches in Multi-Phase Programming of Non-Volatile Memories 5 2006
7,623,386 Reducing program disturb in non-volatile storage using early source-side boosting 5 2006
7,623,387 Non-volatile storage with early source-side boosting for reducing program disturb 7 2006
* 2008/0137,426 NON-VOLATILE STORAGE WITH EARLY SOURCE-SIDE BOOSTING FOR REDUCING PROGRAM DISTURB 2 2006
7,583,535 Biasing non-volatile storage to compensate for temperature variations 24 2006
7,583,539 Non-volatile storage with bias for temperature compensation 9 2006
7,554,853 Non-volatile storage with bias based on selective word line 3 2006
7,525,843 Non-volatile storage with adaptive body bias 7 2006
7,468,919 Biasing non-volatile storage based on selected word line 23 2006
7,468,920 Applying adaptive body bias to non-volatile storage 11 2006
* 2008/0158,976 BIASING NON-VOLATILE STORAGE BASED ON SELECTED WORD LINE 3 2006
* 2008/0158,970 BIASING NON-VOLATILE STORAGE TO COMPENSATE FOR TEMPERATURE VARIATIONS 8 2006
* 2008/0158,992 NON-VOLATILE STORAGE WITH ADAPTIVE BODY BIAS 4 2006
* 2008/0158,975 NON-VOLATILE STORAGE WITH BIAS FOR TEMPERATURE COMPENSATION 10 2006
* 2008/0158,960 APPLYING ADAPTIVE BODY BIAS TO NON-VOLATILE STORAGE 2 2006
7,577,037 Use of data latches in cache operations of non-volatile memories 5 2007
* 2007/0109,867 Use of Data Latches in Cache Operations of Non-Volatile Memories 19 2007
7,551,484 Non-volatile memory and method with reduced source line bias errors 0 2007
* 2007/0109,889 Non-Volatile Memory and Method With Reduced Source Line Bias Errors 1 2007
7,428,171 Non-volatile memory and method with improved sensing 0 2007
* 2007/0109,847 Non-Volatile Memory and Method With Improved Sensing 1 2007
7,391,645 Non-volatile memory and method with compensation for source line bias errors 5 2007
7,391,646 Non-volatile memory and method with control gate compensation for source line bias errors 3 2007
7,295,473 System for reducing read disturb for non-volatile storage 14 2007
* 2007/0153,573 SYSTEM FOR REDUCING READ DISTURB FOR NON-VOLATILE STORAGE 1 2007
7,904,793 Method for decoding data in non-volatile storage using reliability metrics based on multiple reads 35 2007
7,797,480 Method for reading non-volatile storage using pre-conditioning waveforms and modified reliability metrics 3 2007
* 2008/0250,300 METHOD FOR DECODING DATA IN NON-VOLATILE STORAGE USING RELIABILITY METRICS BASED ON MULTIPLE READS 52 2007
* 2008/0244,162 METHOD FOR READING NON-VOLATILE STORAGE USING PRE-CONDITIONING WAVEFORMS AND MODIFIED RELIABILITY METRICS 11 2007
7,606,071 Compensating source voltage drop in non-volatile storage 7 2007
7,606,072 Non-volatile storage with compensation for source voltage drop 2 2007
7,606,079 Reducing power consumption during read operations in non-volatile storage 6 2007
* 2008/0266,975 NON-VOLATILE STORAGE WITH REDUCED POWER CONSUMPTION DURING READ OPERATIONS 4 2007
* 2008/0266,973 REDUCING POWER CONSUMPTION DURING READ OPERATIONS IN NON-VOLATILE STORAGE 24 2007
7,440,327 Non-volatile storage with reduced power consumption during read operations 6 2007
7,463,522 Non-volatile storage with boosting using channel isolation switching 1 2007
7,460,404 Boosting for non-volatile storage using channel isolation switching 6 2007
* 2008/0279,008 NON-VOLATILE STORAGE WITH BOOSTING USING CHANNEL ISOLATION SWITCHING 3 2007
* 2008/0279,007 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 1 2007
7,447,081 Methods for improved program-verify operations in non-volatile memories 21 2007
* 2007/0230,250 Methods for Improved Program-Verify Operations in Non-Volatile Memories 1 2007
7,545,678 Non-volatile storage with source bias all bit line sensing 7 2007
7,539,060 Non-volatile storage using current sensing with biasing of source and P-Well 1 2007
7,532,516 Non-volatile storage with current sensing of negative threshold voltages 3 2007
7,489,554 Method for current sensing with biasing of source and P-well in non-volatile storage 3 2007
* 2009/0003,068 METHOD FOR SOURCE BIAS ALL BIT LINE SENSING IN NON-VOLATILE STORAGE 2 2007
7,471,567 Method for source bias all bit line sensing in non-volatile storage 13 2007
7,447,079 Method for sensing negative threshold voltages in non-volatile storage using current sensing 26 2007
* 2008/0247,239 METHOD FOR CURRENT SENSING WITH BIASING OF SOURCE AND P-WELL IN NON-VOLATILE STORAGE 0 2007
* 2008/0247,253 NON-VOLATILE STORAGE WITH TEMPERATURE COMPENSATION FOR BIT LINE DURING SENSE OPERATIONS 21 2007
7,894,269 Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells 6 2007
7,652,929 Non-volatile memory and method for biasing adjacent word line for verify during programming 14 2007
* 2009/0073,771 Non-Volatile Memory and Method for Biasing Adjacent Word Line for Verify During Programming 13 2007
* 2008/0019,188 Nonvolatile Memory and Method for Compensating During Programming for Perturbing Charges of Neighboring Cells 26 2007
7,577,034 Reducing programming voltage differential nonlinearity in non-volatile storage 5 2007
* 2009/0080,263 REDUCING PROGRAMMING VOLTAGE DIFFERENTIAL NONLINEARITY IN NON-VOLATILE STORAGE 10 2007
7,492,634 Method for programming of multi-state non-volatile memory using smart verify 10 2007
7,688,638 Faster programming of multi-level non-volatile storage through reduced verify operations 6 2007
* 2009/0147,573 FASTER PROGRAMMING OF MULTI-LEVEL NON-VOLATILE STORAGE THROUGH REDUCED VERIFY OPERATIONS 18 2007
7,609,556 Non-volatile memory with improved program-verify operations 4 2007
7,463,528 Temperature compensation of select gates in non-volatile memory 25 2007
7,460,407 Temperature compensation of voltages of unselected word lines in non-volatile memory based on word line position 8 2007
* 2008/0094,908 TEMPERATURE COMPENSATION OF VOLTAGES OF UNSELECTED WORD LINES IN NON-VOLATILE MEMORY BASED ON WORD LINE POSITION 4 2007
* 2008/0094,930 TEMPERATURE COMPENSATION OF SELECT GATES IN NON-VOLATILE MEMORY 2 2007
7,764,547 Regulation of source potential to combat cell source IR drop 9 2007
7,701,761 Read, verify word line reference voltage to track source level 5 2007
* 7,593,265 Low noise sense amplifier array and method for nonvolatile memory 12 2007
7,468,921 Method for increasing programming speed for non-volatile memory by applying direct-transitioning waveforms to word lines 0 2008
7,593,277 Method for compensated sensing in non-volatile memory 1 2008
* 2008/0117,701 Method For Compensated Sensing In Non-Volatile Memory 4 2008
7,495,956 Reducing read disturb for non-volatile storage 15 2008
7,447,065 Reducing read disturb for non-volatile storage 11 2008
7,440,318 Reducing read disturb for non-volatile storage 16 2008
* 2008/0137,411 REDUCING READ DISTURB FOR NON-VOLATILE STORAGE 1 2008
7,577,026 Source and drain side early boosting using local self boosting for non-volatile storage 1 2008
7,606,076 Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise 11 2008
* 2008/0247,241 SENSING IN NON-VOLATILE STORAGE USING PULLDOWN TO REGULATED SOURCE VOLTAGE TO REMOVE SYSTEM NOISE 5 2008
7,915,664 Non-volatile memory with sidewall channels and raised source/drain regions 0 2008
* 2009/0261,398 NON-VOLATILE MEMORY WITH SIDEWALL CHANNELS AND RAISED SOURCE/DRAIN REGIONS 7 2008
8,051,240 Compensating non-volatile storage using different pass voltages during program-verify and read 7 2008
* 2009/0282,184 COMPENSATING NON-VOLATILE STORAGE USING DIFFERENT PASS VOLTAGES DURING PROGRAM-VERIFY AND READ 6 2008
7,719,902 Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage 3 2008
7,957,197 Nonvolatile memory with a current sense amplifier having a precharge circuit and a transfer gate coupled to a sense node 8 2008
* 2009/0296,488 High Speed Sense Amplifier Array and Method for Nonvolatile Memory 16 2008
7,499,324 Non-volatile memory and method with control gate compensation for source line bias errors 11 2008
7,800,956 Programming algorithm to reduce disturb with minimal extra time penalty 12 2008
7,796,430 Non-volatile memory using multiple boosting modes for reduced program disturb 6 2008
* 2009/0010,065 NON-VOLATILE MEMORY USING MULTIPLE BOOSTING MODES FOR REDUCED PROGRAM DISTURB 1 2008
7,733,703 Method for non-volatile memory with background data latch caching during read operations 3 2008
* 2009/0067,253 Method for Non-Volatile Memory With Background Data Latch Caching During Read Operations 7 2008
7,751,244 Applying adaptive body bias to non-volatile storage based on number of programming cycles 3 2008
8,130,552 Multi-pass programming for memory with reduced data storage requirement 2 2008
* 2010/0061,151 MULTI-PASS PROGRAMMING FOR MEMORY WITH REDUCED DATA STORAGE REQUIREMENT 130 2008
7,633,802 Non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages 82 2008
* 2009/0103,356 NON-REAL TIME REPROGRAMMING OF NON-VOLATILE MEMORY TO ACHIEVE TIGHTER DISTRIBUTION OF THRESHOLD VOLTAGES 5 2008
7,936,602 Use of data latches in cache operations of non-volatile memories 2 2009
7,852,678 Non-volatile memory with improved sensing by reducing source line current 4 2009
7,978,526 Low noise sense amplifier array and method for nonvolatile memory 10 2009
* 2010/0008,148 Low Noise Sense Amplifier Array and Method for Nonvolatile Memory 10 2009
8,284,606 Compensating for coupling during programming 4 2009
8,179,723 Non-volatile memory with boost structures 2 2010
* 2010/0157,678 NON-VOLATILE MEMORY WITH BOOST STRUCTURES 4 2010
8,054,681 Read, verify word line reference voltage to track source level 0 2010
8,023,322 Non-volatile memory and method with reduced neighboring field errors 1 2010
* 2010/0182,831 Non-Volatile Memory And Method With Reduced Neighboring Field Errors 2 2010
8,000,146 Applying different body bias to different substrate portions for non-volatile storage 1 2010
8,036,041 Method for non-volatile memory with background data latch caching during read operations 10 2010
* 8,050,126 Non-volatile memory with improved sensing by reducing source line current 0 2010
* 2011/0075,480 Non-Volatile Memory With Improved Sensing By Reducing Source Line Current 2 2010
8,472,280 Alternate page by page programming scheme 15 2010
8,468,424 Method for decoding data in non-volatile storage using reliability metrics based on multiple reads 1 2011
* 2011/0131,473 Method For Decoding Data In Non-Volatile Storage Using Reliability Metrics Based On Multiple Reads 17 2011
8,400,839 Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells 5 2011
* 2011/0141,818 Nonvolatile Memory and Method for Compensating During Programming for Perturbing Charges of Neighboring Cells 2 2011
8,169,831 High speed sense amplifier array and method for non-volatile memory 2 2011
* 2011/0205,804 High Speed Sense Amplifier Array and Method for Non-Volatile Memory 6 2011
8,154,923 Non-volatile memory and method with power-saving read and program-verify operations 1 2011
8,300,472 Low noise sense amplifier array and method for nonvolatile memory 0 2011
8,164,957 Reducing energy consumption when applying body bias to substrate having sets of nand strings 2 2011
8,300,457 Non-volatile memory and method with reduced neighboring field errors 0 2011
8,351,269 Method for non-volatile memory with background data latch caching during read operations 1 2011
8,705,293 Compact sense amplifier for non-volatile memory suitable for quick pass write 6 2011
8,630,120 Compact sense amplifier for non-volatile memory 2 2011
8,300,473 Non-volatile memory with improved sensing by reducing source line current 0 2011
8,542,529 Non-volatile memory and method with power-saving read and program-verify operations 0 2012
8,995,211 Program condition dependent bit line charge rate 0 2012
8,411,507 Compensating for coupling during programming 1 2012
9,293,195 Compact high speed sense amplifier for non-volatile memory 0 2012
9,076,545 Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution 0 2013
8,971,141 Compact high speed sense amplifier for non-volatile memory and hybrid lockout 0 2013
8,966,350 Providing reliability metrics for decoding data in non-volatile storage 0 2013
9,177,663 Dynamic regulation of memory array source line 1 2013
9,368,224 Self-adjusting regulation current for memory array source line 0 2014
9,208,895 Cell current control through power supply 0 2014
9,349,468 Operational amplifier methods for charging of sense amplifier internal nodes 0 2014
 
Micron Technology, Inc. (2)
7,423,476 Current mirror circuit having drain-source voltage clamp 4 2006
7,705,664 Current mirror circuit having drain-source voltage clamp 4 2008
 
PT 259, LLC (1)
8,559,222 Nonvolatile semiconductor memory 4 2013
 
Legend Design Technology, Inc. (1)
* 2005/0049,845 Verification and characterization of noise margin in integrated circuit designs 0 2003
 
KABUSHIKI KAISHA TOSHIBA (12)
7,365,018 Fabrication of semiconductor device for flash memory with increased select gate width 6 2005
* 2007/0148,973 Fabrication of semiconductor device for flash memory with increased select gate width 2 2005
7,692,987 Semiconductor storage device 3 2008
* 2008/0291,743 SEMICONDUCTOR STORAGE DEVICE 7 2008
8,009,470 Nonvolatile semiconductor memory 7 2009
* 2010/0135,078 NONVOLATILE SEMICONDUCTOR MEMORY 3 2009
8,203,888 Non-volatile semiconductor storage device 6 2010
8,223,543 Nonvolatile semiconductor memory 1 2011
8,649,223 Semiconductor storage device 0 2012
8,787,087 Semiconductor memory device controlling operation timing of the sense circuit 2 2012
8,477,534 Nonvolatile semiconductor memory 6 2012
8,750,039 Nonvolatile semiconductor memory 0 2013
 
SANDISK IL LTD. (8)
7,679,965 Flash memory with improved programming precision 2 2007
7,660,166 Method of improving programming precision in flash memory 2 2007
* 2008/0181,000 Method Of Improving Programming Precision In Flash Memory 37 2007
* 2008/0180,996 Flash Memory With Improved Programming Precision 7 2007
8,073,648 Measuring threshold voltage distribution in memory using an aggregate characteristic 6 2007
7,613,045 Operation sequence and commands for measuring threshold voltage distribution in memory 27 2007
* 2009/0135,646 OPERATION SEQUENCE AND COMMANDS FOR MEASURING THRESHOLD VOLTAGE DISTRIBUTION IN MEMORY 7 2007
* 2008/0285,351 MEASURING THRESHOLD VOLTAGE DISTRIBUTION IN MEMORY USING AN AGGREGATE CHARACTERISTIC 137 2007
* Cited By Examiner

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
11.5 Year Payment $7400.00 $3700.00 $1850.00 Nov 16, 2017
Fee Large entity fee small entity fee micro entity fee
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00