Integrated circuit that processes communication packets with a buffer management engine having a pointer cache
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United States of America Patent
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May 16, 2006
Grant Date -
N/A
app pub date -
Aug 16, 2000
filing date -
Aug 17, 1999
priority date (Note) -
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Abstract
An integrated circuit processes communication packets and comprises a pointer cache and control logic. The pointer cache store pointers that correspond to external buffers that are external to the integrated circuit and configured to store the communication packets. The control logic allocates the external buffers as the corresponding pointers are read from the pointer cache and de-allocates the external buffers as the corresponding pointers are written back to the pointer cache.
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