Digital filter and method for performing a multiplication based on a look-up table
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United States of America Patent
Stats
-
May 16, 2006
Grant Date -
Aug 29, 2002
app pub date -
Oct 3, 2001
filing date -
Apr 14, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A digital and a multiplication method are described, which lead to an efficient architecture for a hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are performed by addressing look-up tables in which corresponding multiplication results are prestored. The size of the look-up tables is reduced by storing only those multiplication results which cannot be obtained by a shifting operation performed on the other pre-stored multiplication results, the input sample data, or the delayed sample data. Thereby, the size of the look-up tables can be compressed significantly such that an implementation of large digital filters into FPGAs is possible.
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- Non-US Classification not provided for expired patents
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