Multi-processing memory duplication system
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United States of America Patent
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May 16, 2006
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N/A
app pub date -
Dec 19, 2002
filing date -
Dec 29, 2001
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Abstract
Embodiments of the present invention relate to an apparatus including a first processor module, a second processor module, and a bus. The bus is coupled to the first processor module and the second processor module. The bus is configured to transmit both processor related communication and memory related communication. In embodiments, the first processor module includes a first central processing unit and the second processing module includes a second central processing unit. Accordingly, in embodiments of the present invention, a single bus can be used to communicate between processors and memories. The present invention is useful for real time duplication of memory, high speed duplication of memory, and/or a coherency check of memory between a first processing module and a second processing module.
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