Multi-chip package having repairable embedded memories on a system chip with an EEPROM chip storing repair information
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United States of America Patent
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May 30, 2006
Grant Date -
N/A
app pub date -
Feb 19, 2005
filing date -
Feb 19, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
A die with embedded memory is packaged together in a same dual-chip package with an EEPROM die. Defects in the embedded memory can be repaired using redundant rows or columns. A built-in self-test (BIST) controller locates defects and a repair image is generated. The repair image is stored in non-volatile memory in the EEPROM die. At power-up, the repair image is copied from the EEPROM die to a volatile repair RAM in the embedded memory die. The redundant rows or columns are mapped to replace defective rows/columns using the repair image in the volatile repair RAM. Although the embedded-memory die has only volatile memory and no fuses, its embedded memory can be repaired using the repair map from the non-volatile EEPROM die. Since the EEPROM die is in the same dual-chip package as the embedded memory die, the repair map is always available.
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