Nonvolatile semiconductor memory
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United States of America Patent
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May 30, 2006
Grant Date -
May 19, 2005
app pub date -
Jul 12, 2004
filing date -
Jul 15, 2003
priority date (Note) -
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Abstract
The number of electrons existing in a channel region within a NAND cell unit is reduced, and erroneous write-in characteristics are improved by the present invention. A nonvolatile semiconductor memory includes a control gate line drive circuit, which writes simultaneously in all memory cell transistors connected to a selected control gate line, performs write-in by maintaining a low channel voltage for a selected memory transistor in a selected memory cell unit when a plus voltage is applied to the selected control gate line, and restricts write-in utilizing a voltage self-boosted from the channel voltage for an unselected memory transistor.
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