Semiconductor device
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United States of America Patent
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May 30, 2006
Issued Date -
N/A
app pub date -
Dec 13, 2004
filing date -
Nov 27, 2000
priority date (Note) -
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Abstract
A dummy cell includes a plurality of first memory cells MC for storing '1' or '0', arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing '1' or '0', arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing '0', arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
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