Apparatus for random access memory array self-test
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United States of America Patent
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May 30, 2006
Grant Date -
Jun 5, 2003
app pub date -
Dec 5, 2001
filing date -
Dec 5, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An apparatus for the on-chip testing of random access memory arrays. In representative embodiments, embedded circuitry provides the ability to test random access memory arrays on-chip without requiring substantial area on the chip. The circuits are inherently located closer to the tested area which reduces propagation delay errors. These advantages have been obtained by locating the circuitry necessary to perform such test in the addressing and input/output blocks of the RAM.
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