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Abstract

An integrated semiconductor memory (1) has a multiplicity of memory cells (Z) and first lines (10) and second lines (20) that can be used to actuate the memory cells (Z). The path of each of the first lines (10) contains a respective device (5) that permits actuation of memory cells exclusively in the region of first subsections (I) of the first lines (10). The devices (5) can be set such that they bring about only partial decoupling of the second subsections (II) of the first lines (10) from the slatter's first subsections (I), with memory cells either in the region of the first subsections (I) only or in the region of both subsections (I, II) being able to be actuated, depending on the choice of a relatively short or a relatively long access time to the memory cells. This allows subregions of the semiconductor memory to be used for power-saving and faster memory operation.

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First Claim