Asynchronous memory using source synchronous transfer and system employing the same
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United States of America Patent
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Jun 6, 2006
Grant Date -
Feb 5, 2004
app pub date -
Mar 25, 2003
filing date -
Jul 30, 2002
priority date (Note) -
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Abstract
A memory for storing data information and/or a controller for controlling read/write operations of the memory based on a source synchronous interface are provided. During the read/write operations, a command and an address are provided to the memory together with the first strobe signal. The memory may latch the command and address in response to the first strobe signal. During a read operation, the memory responds to a received second strobe signal to generate a third strobe signal. The memory outputs data from the memory and the third strobe signal, for example, so that the output data may be latched with the third strobe signal by the memory controller.
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