Method and apparatus for generating jitter test patterns on a high performance serial bus
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United States of America Patent
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Jun 6, 2006
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app pub date -
Mar 16, 2004
filing date -
Apr 21, 2000
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Abstract
The present invention provides a computer readable medium containing instructions for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The instructions are executed to generate jitter test patterns by disabling the transmitter data scrambler of the second device; clear the port_error register of the device under test; and send a test pattern to said device under test.
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