Methods for designing PLD architectures for flexible placement of IP function blocks
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United States of America Patent
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Jun 6, 2006
Issued Date -
N/A
app pub date -
Jun 11, 2003
filing date -
May 6, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.
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