NAND string wordline delay reduction
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United States of America Patent
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-
Jun 20, 2006
Grant Date -
Feb 9, 2006
app pub date -
Aug 4, 2004
filing date -
Aug 4, 2004
priority date (Note) -
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Abstract
An improved NAND Flash memory and word line selection method has been described, that takes advantage of the asymmetric nature of the word line to word line capacitive coupling to reduce word line selection delay by driving the adjacent word lines to a higher initial voltage and then reducing it to the final target voltage. As the capacitive coupling in between the NAND word lines is a larger effect when the voltages are being lowered, this has the effect of damping out the voltage initially induced in the lower voltage word line by the rising voltages on the adjacent word lines, reducing the overall selection time.
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