Semiconductor devices including protective layers on active surfaces thereof

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7067901
APP PUB NO 20030201531A1
SERIAL NO

10435327

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Abstract

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A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. A plurality of discrete protective structures may be formed on corresponding semiconductor devices that are carried by a large-scale semiconductor substrate. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INCBOISE ID

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farnworth, Warren M Nampa, ID 855 33798
Wood, Alan G Boise, ID 415 23368

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