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Abstract

A delay locked loop includes a forward path, a feedback path, a phase detector, logic, and a dither circuit. The forward path includes a delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal. The feedback path is configured to provide a feedback clock signal based on the output clock signal. The phase detector is configured to compare the input clock signal and the feedback clock signal and generate a shift signal if the output clock signal is not in phase with the input clock signal. The logic is coupled to the delay line and configured to receive the shift signal and control the time interval based on the shift signal. The dither circuit is coupled to the delay line and configured to introduce a delay responsive to an assertion of a test mode enable signal.

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First Claim