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Abstract

A plurality of virtual memory spaces is implemented in a computer system designed to be binary-compatible with one or a plurality of foreign architectures. A single primary virtual memory space, designated as the native VM space, contains native codes directly executable by the host microprocessor, such as the binary translated codes and the binary translation process/system itself. One or a plurality of secondary virtual memory spaces, designated as the foreign VM space(s), contain foreign data and codes (to be translated into binary translated codes in the primary VM space) only, hence encompassing no native code executable by the host microprocessor directly. In one embodiment, each foreign architecture supported by the host microprocessor through the binary translation process is provided its own secondary VM space; hence the number of the secondary VM spaces supported equals the number of the foreign architectures supported. While all VM spaces are directly supported by the host microprocessor MMU hardware including, for example, corresponding address translation schemes and exception delivery, their properties may differ significantly, allowing for the primary VM to exploit the host microprocessor architecture benefits to the fullest possible extent at the same time as the secondary VM spaces mimic VM spaces of the corresponding foreign microprocessor architectures. After corresponding address translation, addresses from both the primary and the secondary VM space(s) are mapped to a single physical address space of the host microprocessor.

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First Claim