Space-saving packaging of electronic circuits
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United States of America Patent
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Jul 4, 2006
Grant Date -
Oct 16, 2003
app pub date -
Mar 12, 2003
filing date -
Jan 16, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus and packaging method for stacking a plurality of integrated circuit substrates, i.e., substrates having integrated circuits formed as integral portions of the substrates, which provides interconnection paths through the substrates to simplify electrical connections between the integrated circuits while facilitating minimization of the volume and customization of the three dimensional package size to conform to the available internal space within a housing, e.g., one used in an implantabie device where package volume is at a premium. Furthermore, an internal cavity can be created by the stacked formation that is suitable for mounting of a surface mount device, e.g., a crystal or the like.
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