Intelligent wait methodology
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United States of America Patent
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Jul 11, 2006
Grant Date -
Nov 24, 2005
app pub date -
Apr 11, 2003
filing date -
Apr 11, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A central processing unit (CPU) configured to apply an intelligent wait methodology is provided. The CPU includes a chip select module that defines a chip select signal associated with an external device. The chip select module includes an address space configured to store addresses associated with the external device. The address space provides an address section. The address section is associated with the external device and is subdivided into address sub-sections associated with an address range and assigned through the chip select signal. The address sub-sections are configured to determine a bus cycle based on an association with either the CPU monitoring a wait line between the CPU and the external device or the CPU waiting for a number of wait states. A device and a method for optimizing a bus cycle length between a CPU and an external device in communication with the CPU are provided.
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