Quad flat no-lead (QFN) grid array package, method of making and memory module and computer system including same
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United States of America Patent
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Jul 11, 2006
Grant Date -
Jun 17, 2004
app pub date -
Dec 5, 2003
filing date -
Aug 6, 2001
priority date (Note) -
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Abstract
A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.
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