METHODS AND APPARATUS FOR IMPLEMENTING A POWER DOWN IN A MEMORY DEVICE
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United States of America Patent
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Jul 18, 2006
Grant Date -
Aug 10, 2006
app pub date -
Feb 4, 2005
filing date -
Feb 4, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
A power down is implemented in a memory device capable of performing a read operation in which data and a data strobe signal are supplied as outputs. The power down techniques includes generating a first signal for preventing the data from being supplied as an output of the memory device, generating a second signal for causing the data strobe signal to remain in a predetermined state, and generating a third signal for preventing the data strobe signal in the predetermined state from being supplied as an output of the memory device.
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