Method and apparatus for identifying optimized via locations

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United States of America Patent

PATENT NO 7080329
SERIAL NO

10288870

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Abstract

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Some embodiments of the invention provide a method of identifying a via between at least two layers of a multi-layer design layout. The method identifies a region within which the via should be located. It then formulates an optimization problem for identifying a location of the via in the region. It then solves the optimization problem to find an optimized location for the via.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC A DELAWARE CORPORATION2655 SEELY AVE BUILDING 5 MS 5B1 SAN JOSE CA 95134

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Caldwell, Andrew Santa Clara, CA 120 1490
Teig, Steven Menlo Park, CA 333 6577

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