Importance

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Abstract

In the display device having the retaining circuit for holding the digital image data at the pixel element, the power voltage supplied to the retaining circuit 110 is set up to be at the minimum level for the retaining circuit to hold the data during the data writing period, but the voltage supplied to the retaining circuit is raised by the voltage booster 95 upon the completion of the data writing. The retaining circuit 110 takes in the digital image signal fed from the drain signal line 61 in response to the signal fed from the gate signal line 51 and holds the digital image signal. Then, the display is carried out according to the signal held by the retaining circuit 110. By this, the erroneous writing of the data to the retaining circuit is prevented. The reduction of the electric power consumption and the high density integration of the pixel elements are also possible.

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First Claim